1. Field of the Invention
The present invention relates to a BGA-type multilayer circuit wiring board on which semiconductor chips are mounted.
2. Background Art
Recently developed, some semiconductor devices such as semiconductor large-scale integrated circuits (LSI) have an operation speed on a GHz level as clock frequency. Such high-speed semiconductor devices have a high integration degree of transistors, in which, therefore, the number of input/output terminals may be over 1000.
For mounting such a multi-terminal semiconductor device on a printed wiring board, a multilayer circuit wiring board is disposed between the semiconductor device and the printed board, and it acts for electric interconnection between the two. The multilayer circuit wiring board has an extremely thinner layer structure than a printed board and has a microfabricated line-and-space wiring pattern in order that it may satisfy good interconnection with the terminals of such a high-density semiconductor device.
For example, BGA (ball grid array) or CSP (chip size package) multilayer circuit wiring boards are now widely in practical use in the art.
For satisfying the recent requirements for higher density packaging and higher operation frequency, a technique of fabricating a multilayer circuit wiring board has become developed, which comprises laminating polyimide resin films each with a wiring layer formed thereon, without a core board, so as to reduce the overall thickness of the resulting multilayer circuit wiring board and to shorten the interlayer connection length thereof enough for high-frequency operation.
FIG. 2A is a partly-cut schematic cross-sectional view showing an example of a BGA-type multilayer circuit wiring board having a 4-layered structure; and FIG. 2B is a partly-cut schematic cross-sectional view showing an example of the multilayer circuit wiring board 200 mounted on a printed wiring board 70 with solder balls 61.
The multilayer circuit wiring board 200 comprises an insulating substrate 11 with a wiring layer 21 and a wiring layer 22 formed on both surfaces thereof, in which the wiring layer 21 and the wiring layer 22 are electrically connected to each other via a filled via 23. An electrode pad for solder bump 41, which is for semiconductor chip connection, is formed on one surface of the structure as interrupted by an insulating layer 31 formed therebetween, while an electrode pad for solder ball 45 is formed on the other surface thereof, which is for connection of the structure to a printed wiring board.
The electrode pad for solder bump 41 is electrically connected to the wiring layer 22 via a filled via 42; and the electrode pad for solder ball 45 is to the wiring layer 21 via a filled via 46 at the center of the electrode pad for solder ball 45.
In the region except the electrode pad for solder bump 41 and the electrode pad for solder ball 45, formed are a solder resist layers 51 and 52.
FIG. 4 shows an ordinary package structure comprising the above-mentioned multilayer circuit wiring board 200.
On the upper surface of the multilayer circuit wiring board 200, mounted is a semiconductor chip 71 by solder bumps 72. Since the multilayer circuit wiring board 200 is thin and may be readily warped, a frame plate, generally referred to as a stiffener 91, is often fitted around the semiconductor chip 71. To the upper surface of the chip, a radiating plate, generally referred to as a lid 92, is stuck (for example, see Patent Reference 1).
On the lower surface of the multilayer circuit wiring board 200, a large number of solder balls are formed in array. In this condition, this is finally mounted on a printed circuit board 70 via the solder balls 61.
A problem with the multilayer circuit wiring board without the core board of the type is that, since the multilayer circuit wiring board is thin, it may be deformed and stress may occur in the wiring layer inside the multilayer circuit wiring board.
In particular, stress may readily concentrate in the filled vias acting for electric interconnection of the wiring layers.
Electric wiring becomes minute, and a diameter of filed via tends to shrink to satisfy a required electrical characteristic. Therefore the stress that filled via is born becomes small, and electric link reliability falls.
Different from ordinary built-up boards, the multilayer circuit wiring board of the type is so designed that solder balls are directly connected to the lower surface of the multilayer circuit wiring board, not via a thin printed board (core board) therebetween, as so mentioned in the above.
Accordingly, as in FIG. 2A, in the filled via 46 formed inside the solder ball connection pad 45, there may often occur thermal deformation owing to the difference in the thermal expansion coefficient between the multilayer circuit wiring board and the solder ball or the printed board, and it may cause a problem in point of the circuit interconnection reliability.
In a BGA type multilayer circuit wiring board having the electric wiring layers which the number of the layer is more than 4, there are much number of filled vias. Even more particularly, a difference between coefficient of thermal expansion of the central insulator layer and coefficient of thermal expansion of the adhesive line laminated on the insulator layer is large. Therefore, by reason of thermal stress, electric link reliability falls.
Besides, when solder balls are lead-free solder, temperature in the mounting is about 260 degrees Celsius. In other words, this temperature is higher than the temperature (about 220 degrees Celsius) in mounting of a conventional eutectic solder. In addition, lead-free solder is harder than a eutectic solder. Difference between coefficient of thermal expansion of the lead-free solder and coefficient of thermal expansion of the multilayered circuit wiring board is larger. When a multilayered circuit wiring board is mounted on a circuit board, as a whole, stress is zero. In the case of the mounting with lead-free solder, difference between coefficient of thermal expansion in the mounting and coefficient of thermal expansion at the time of use is larger. Thus, as for the mounting with lead-free solder, stress to a multilayered circuit wiring board is larger.
Patent Reference 1: JP-A 2001-110926